1. Field of the Invention
This invention relates to fabrication of integrated circuits and, in particular, to the fabrication of integrated circuits involving conductive regions.
2. Art Background
In the fabrication of integrated circuits, generally multiple layers of material are formed and electrical interconnects are made between these layers. These interconnects are generally formed by etching a via or window through an intermediate layer, e.g., a dielectric layer, and filling the conduit with a metallic material to establish a conduction path. An electrically conductive pattern produced on the overlying layer then provides the desired electrical circuit connection to regions in the underlying layer.
At design rules less than 0.5 micron, the aspect ratio of the via or window defining the interconnects is generally greater than 3 and often as high as 5 to 10. (Aspect ratio is the ratio of height to width of the opening defining the interconnect.) For such high aspect ratios, it is often a challenge to fill the via completely with the metallization material and to assure good electrical continuity between the adjoining conducting layers. Seams and voids resulting from poor filling not only yield a high via resistance but also invite entrapment of contaminants in subsequent processing steps that, in turn, often lead to reliability problems. To avoid gaps and the attendant problems, chemical vapor deposition (CVD) procedures are typically employed. Since CVD occurs at a surface from a gas, filling of high aspect ratio interconnects is possible. However, CVD for metals such as aluminum involves many difficulties and often requires significant care. (See U.S. Pat. No. 5,008,217, dated Apr. 16, 1991.) Use of directional sputtering has also been investigated but is extremely difficult to control, especially at small dimensions and high aspect ratios.
Sometimes, it is also desirable that the interconnects be filled during formation of the metal pattern on the overlying layer. In this case, pattern forming is generally accomplished by blanket deposition to fill the interconnects and to produce an overlying layer of metal, with subsequent delineation of this layer by etching through a photolithography defined mask.
Although aluminum metallization patterns together with aluminum or refractive metal interconnects have almost uniformly been employed in integrated circuit devices for strict design rules, i.e., less than 0.5 micron, at such design rules the time delay in the circuit attributed to the delay in the interconnects becomes a significant factor. To reduce this delay, use of copper with its lower electrical resistivity has been proposed. (The specific resistivity of pure copper is 1.7 microohm-cm, that for aluminum is 2.8, and 3.3 is typical for copper-containing aluminum alloys presently used for VLSI metallization.) Metallization with a copper material, i.e., a material of at least 90 mole percent copper also offers other advantages. With smaller device dimensions, concomitant current density increase in the narrowed aluminum conductors often engenders reliability problems due to electromigration, i.e. distortion of the lines in the pattern. Copper appears to be less susceptible to such problems.
However, implementation of copper metallization for submicron device fabrication has been extremely difficult. Copper has a tendency to diffuse into silicon and silicon dioxide. The adhesion of copper is known to be notoriously poor. It is also extremely difficult to etch copper to produce desired fine line (0.5 .mu.m or finer) circuit patterns. Comparable procedures such as chemical vapor deposition for depositing copper suffer many complications relating to selectivity and processing temperatures. Therefore, although use of copper in the metallization of integrated circuits might be theoretically desirable for shrinking design rules, suitable means are still lacking.